| 摘要 |
<p>A pipeline system for a microprogram control unit is arranged such that a command is pre-read in order to prevent the generation of any dummy cycle and attain a higher speed, and at the same time when a program counter specifies an address, a command corresponding to the specified address in held in a pipeline register. Further, when a conditional branch instruction is issued, all of the commands which may be subsequently executed are pre-read in parallel, and a command to be executed is selected from the pre-read commands.</p> |
