| 摘要 |
PURPOSE:To obtain always a vertical drive pulse with a fixed width by providing a D-FF and a T-FF to which a clock pulse from the 1st frequency divider is inputted to match the release time of a reset pulse to the phase of the clock pulse. CONSTITUTION:A signal from a voltage controlled oscillator 4 is frequency- divided by the 1st frequency divider circuit 5, becomes a clock pulse and is inputted to the D-FF17 and the T-FF18. The clock frequency-divided by 1/2 at the FF18 activates the 2nd frequency divider circuit 9, its frequency division output is inputted to an FF13, a Q output of the FF13 is inputted to an AND circuit 16 and also resets the FF18. A composite video signal is inputted to a terminal 2, a vertical trigger pulse separated by a synchronizing separator circuit 1 is inputted to the circuit 16 and an output of the circuit 16 is fed to the FF17 via an OR circuit 15. The horizontal synchronizing signal separated by the circuit 1 controls the oscillator 4 via an AFC circuit 3 at the same time so as to take synchronism. The reset of the FF18 is released by the Q output of the FF17, the output of the FF18 activates the circuit 9 and the vertical drive pulse having a fixed width with prescribed frequency division is outputted to a vertical deflection circuit 11. |
