| 摘要 |
PURPOSE:To deliver the high-speed data of a digital signal, etc. with high stability by defining a variable delay circuit as a unit circuit and then using plural units of said unit circuits to set various amounts of delay. CONSTITUTION:The input data IN is supplied to a shift register 11 consisting of registers R1-R16 of 16 stages. The output of each of four-register groups R1- R4, R5-R8, R9-R12 and R13-R16 of the register 11 is supplied to each of selectors 21-24 of a selector block 12. The outputs of selectors 21-24 are supplied to a selector 25 via registers R21-R24. While 4-bit selection signals S1-S4 are supplied to registers 31 and 34 of a detector block 13. Then decoders 32 and 35 deliver selection signals P1-P4 and Q1-Q4 respectively. The outputs of selectors 21-24 are selected by signals P1-P4; while the output of the selector 25 is selected by signals Q1-Q4. Thus it is possible to set various amounts of delay, and the high-speed data of a digital signal, etc. is delivered with high stability. |
