| 摘要 |
<p>A mechanism for continually testing a floating point accelerator processor (FPAP) element or other processor element in a suitable multiprocessor system. At least two processors, such as an instruction execution processor(EU) and a FPAP, are connected to a common input bus to concurrently receive the same information (opcodes and operands). Both the EU and the FPAP decode the opcodes. When the FPAP decodes an opcode for an operation to be performed by the EU, the FPAP, instead of remaining idle while the EU operates, executes a diagnostic operation. The FPAP selects the particular diagnostic operation to perform in each instance from among a multiplicity of available diagnostic operations. The selection of a diagnostic operation is dependent on the instruction to be executed by the EU; in order to not slow down the overall execution rate of the system, a diagnostic operation is chosen whose execution time is matched to the execution time of the instruction being performed by the EU; that is, a diagnostic operation is selected such that the FPAP will finish the operation before the EU will finish executing its instruction. Operand data supplied to the EU on the input bus is used by the diagnostic operations, to add a degree of randomness to the test signals and permit detection of bits forced to a steady value of zero or one. For some diagnostic operations, one or more variables may be obtained from general purpose registers.</p> |
