发明名称 ADDRESS CONTROL CIRCUIT OF DAD PLAYER
摘要 PURPOSE:To control the address of a memory where symbols read out from a disc are stored by providing the second adding means which adds the reference address outputted from a reference address output means and the relative address outputted from the first adding means. CONSTITUTION:A player reproduces symbols W0-W23, which are written on the disc in accordance with a format shown in a figure, as a music signal. A signal INP is read out from the disc through an optical system is inputted to a receiving circuit 2. A reference address generating circuit 1a outputs a reference address EADR, which is used when symbols U0-U3 outputted from a buffer register 4 are written, and a reference address MADR which is used when symbols U0-U3 in an RAM6 are processed and a signal CAC is outputted. A relative address generating circuit 1b outputs a relative address RADR, and an adder 1c adds the reference address EADR or MADR and the relative address RADR. The output of the adder 1c is supplied as an address signal ADS to an address terminal AD of the RAM6.
申请公布号 JPS6079564(A) 申请公布日期 1985.05.07
申请号 JP19830186104 申请日期 1983.10.05
申请人 NIPPON GAKKI SEIZO KK 发明人 NARISAWA SADAYUKI;TOMIZAWA NORIO
分类号 G11B7/013;G11B20/10;G11B20/12;G11B20/14;G11B20/18 主分类号 G11B7/013
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