Pulsewidth modulated, charge transfer, digital to analog converter

摘要

A microprocessor-driven pulsewidth modulated, charge transfer, digital to analog converter for use in a sample data system. During the sample period a capacitor is charged to an error signal value which is the difference between the output of an operational amplifier and an average DC voltage proportional to the sampled digital data. During the hold mode, the charge on the capacitor is transferred to a capacitor of smaller value connected between the input and output of the operational amplifier. This provides an error update during the hold period, permitting the circuit to be used with a computer on a time shared basis.