| 摘要 |
PURPOSE:To miniaturize circuit constitution and to attain high speed processing by constituting a digital arithmetic circuit with AND gates, OR gates, a multiplexer, an adder, etc. CONSTITUTION:Multiplier outputting products X0XY0, X1XY1... of inputs X0, X1, X2..., Y0, Y1, Y2... is constituted of arithmetic circuits of even and odd items. Respective arithmetic circuits are provided with AND gates a0, a2 and a1, a3..., OR gates A0, B0 and A1, B1..., multipliers M0, M1..., AND gates b0, b2 and b1, b3... and the sum of the outputs from both the arithmetic circuits is calculated by an adder SIGMA. It is previously discriminated that only a certain number K of continuous integers are ''0''s and others are all ''1''s out of the inputs Y0, Y1, Y3.... The discriminated logical value Si is inputted to odd and even item logical circuits. Thus, the size of the constitution of the digital arithmetic circuit is miniaturized and high speed processing is attained. |
