| 摘要 |
A data transfer system is disclosed which includes a main memory, a memory control unit for controlling the operation of the main memory, a central processing unit, a plurality of direct memory access units each provided with at least two data transfer bus widths, a common data bus line, and a common memory address/control line. A control line is provided for distinguishing between the at least two data transfer bus widths and is only connected between a direct memory access unit provided with the memory control unit, the central processing unit and one of the at least two data transfer bus widths. When data is transferred, using one of the data transfer bus widths, the control line is energized with a control signal which is delivered to the memory control unit. On the other hand, the direct memory access unit which has the other data transfer bus width is not connected to the control line thereby preventing it from becoming energized. The memory control unit controls the operation of a gate circuit between the memory data line which is connected between the main memory and the data bus line and the read data line and generates a write enable signal for effecting a writing of data in byte units in either an even number address or an odd number address thereof.
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