| 摘要 |
PURPOSE:To extend the Vcc margin and perform operations in a high speed by using an intrinsic FET having a weak back gate bias effect as a transfer gate provided between a predecoder and an inverter. CONSTITUTION:A circuit is constituted with a P-channel active load FETT11 whose gate a voltage Vss is given to and at least two FETs T12-T13 connected in series, and enhancement FETs T1 and T2 are substituted with intrinsic N-channel FETs (I-type N-channel FETs) T6 and T7. Since a threshold voltage Vth of the intrinsic FET is about zero (Vth 0V) (that of the enhancement FET is about 0.8V) and the impurity concentration in the channel part is low, therefore the substrate bias effect is weak. Consequently, the potential in a node N2 is charged to the high level sufficiently quickly by FETs T6 and T7, and the Vcc margin is extended and operations are performed in a high speed. |
