发明名称 BUS EXTENDING CIRCUIT
摘要 PURPOSE:To shorten the time required with a composite bus system to decide the right to use a bus by providing a dedicated priority decision circuit to a slave bus. CONSTITUTION:The priority decision circuit consisting of an encoder EC and a decoder DC is provided in a bus extending circuit BA2' provided to the slave bus BUS2, each bus request signal R' from each device connected to the slave bus BUS2 is transmitted to the encoder, and a bus priority input signal P' is sent from the decoder DC to each device. The encoder EC transmits a couple of bus request signals to the priority decision circuit PR provided to a main bus BUS1 in common to all transmitted bus request signals R'. The bus priority input signal P send by the PR for this bus request signal R is transmitted to the decoder DC and converted into a bus priority input signal P' for the selected device on the basis of specific priority.
申请公布号 JPS6069764(A) 申请公布日期 1985.04.20
申请号 JP19830177235 申请日期 1983.09.26
申请人 FUJITSU KK 发明人 ETOU KOUJI;IGI YOUZOU
分类号 G06F13/36;G06F13/40 主分类号 G06F13/36
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