| 摘要 |
A system for resolving the contention between the central processing unit (CPU) and the cathode ray tube (CRT) controller in accessing the video memory array, or video random access memory (RAM), of a data processing system is disclosed. The conventional CPU-CRT controller accessing sequence is modified to provide a CPU access period between successive CRT controller access periods. In addition, arbitration logic is included to provide CRT controller access priority when there is contention between the CPU and the CRT controller. By thus assigning video memory access priority to the CRT controller and increasing the length of the video memory array "read" time during which video information is provided to the system's display device, video display performance is enhanced and display degradation due to video memory array operating speed limitations is essentially eliminated. This approach reduces operating speed criteria of the various components in the data processing system in providing high quality display graphics and improved system operating functions without the need for highly sophisticated and expensive CPU's, RAM's, etc.
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