发明名称 FORMING METHOD FOR MULTILAYER INTERCONNECTION
摘要 PURPOSE:To substantially flatten a stepwise difference between the inside and the outside of a contacting hole by burying the hole with a conductor layer by utilizing a vapor phase reaction selectively covered with metal. CONSTITUTION:An interlayer insulating film 24 is formed over a wiring layer 22 on a primary insulating film 20 formed over the surface of a semiconductor substrate. A contacting hole 24A is formed to expose part of the layer 22 at the film 24. Then, metal is selectively covered only on the wiring layer portion in the hole 24A by a CVD treatment to bury a metal layer 26. In this case, the thickness of the layer 26 is controlled to eliminate the stepwise difference of the hole 24A. Thereafter, the second wiring layer 28 is formed to extend onto the film 24 from the layer 26. Thus, since the contacting hole is buried with conductor such as metal and flattened, an improper conduction or a disconnection can be prevented in the hole.
申请公布号 JPS6065549(A) 申请公布日期 1985.04.15
申请号 JP19830173993 申请日期 1983.09.20
申请人 NIPPON GAKKI SEIZO KK 发明人 YOKOI KATSUYUKI
分类号 H01L21/3205;(IPC1-7):H01L21/88 主分类号 H01L21/3205
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