发明名称 MEMORY ADDRESS CONTROL SYSTEM
摘要 PURPOSE:To shorten a data transfer time and to improve the operation efficiency of a computer system by providing two bank memories into the same address space and to perform the transfer of data as desired just through a transfer action. CONSTITUTION:An I/O address decoder 1 decodes an I/O command given from a CPU, and this decoding output sets or resets an FF circuit 2. The output of the circuit 2 is used as the input of one side of an address modifying circuit 3; while an address signal ADRn is supplied to the other input of the circuit 3. Then the circuit 3 modifies an address, and the transfer of data is performed between the memories under the control of a program. In such a way, a memory can be operated in the same space of >=2 memory modules.
申请公布号 JPS6065357(A) 申请公布日期 1985.04.15
申请号 JP19830173724 申请日期 1983.09.20
申请人 RICOH KK 发明人 YOSHIBA YUTAKA
分类号 G06F12/06;(IPC1-7):G06F12/06 主分类号 G06F12/06
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