| 摘要 |
PURPOSE:To prevent adverse influences generating in the case where a protection circuit absorbs impact noises and thereby to securely prevent latch-up by a method wherein an isolation layer is interposed between the protection layer and the peripheral circuit. CONSTITUTION:An n<-> epitaxial layer 12 on a p<-> substrate 10 in which n<+> layers have been selectively buried is isolated by means of p<+> layers 16; an n<+> take- out layer is formed in an island a4, and p<-> layers 18 in islands a2 and a3. After further isolation by means of oxide films 22, a p type resistance layer BR is formed in the island a1, and a p-base layer 24 in the a4. Next, a poly Si gate electrode 28 is provided in the island a3, p-ch and n-ch MISFET's Qp and Qn being successively formed in each of them, and at the same time an n<+> layer 32 being provided, and accordingly a diode D2 is completed in the island a2, and an n-p-n element Qb in the a4. Since the isolation layers 16 are grounded via substrate, the latch-up can be prevented even when the input protection circuits in the islands a1 and a2 and the CMOS logical circuit for input buffer in the peripheral island a3 become in proximity. Besides, the n<+> buried layers in the a1 and a2 can prevent the action of the parasitic transistor, and further adverse influences to the peripheral logical circuit can be prevented. |
