| 摘要 |
<p>PURPOSE:To accelerate the data reading access time at the release of stand-by by forming latch circuits each of which consists of two inverters in a bit line and a bit inversion line in a semiconductor memory. CONSTITUTION:The semiconductor memory is provided with the 1st inverter of which input terminal is connected to a bit line and output terminal is connected to the input terminal of the 2nd inverter in a static RAM having a bit line and a bit inversion line to which a memory cell in a memory array is connected, the 2nd inverter of which output terminal is connected to the bit line and input terminal is connected to the output terminal of the 1st inverter, the 3rd inverter of which input terminal is connected to the bit inversion line and output terminal is connected to the input terminal of the 4th inverter, and the 4th inverter of which output terminal is connected to the bit inversion line and input terminal is connected to the output terminal of the 3rd inverter. Even at a time immediately after releasing the stand-by state, a sense amplifier can be simply driven at an optimum operating point and high-speed access can be attained.</p> |
