| 摘要 |
PURPOSE:To reduce a operating time of polling by superimposing each interruption signal onto a data line through a buffer assigned with an address when interruption is applied from a peripheral device to a CPU. CONSTITUTION:In applying interruption from plural peripheral devices 2-4 to the CPU1, an interruption signal is inputted to a peripheral control terminal CB1 of PIA (peripheral interface adaptors) 5-7. A terminal IRQB of the PIA5 goes to a low level and a terminal IRQ of the CPU1 goes to a low level through an AND circuit 10 to apply interruption. Each interruption signal is superimposed onto the data line through a buffer 9 to which an address is assigned, and a data is read by selecting the address when the interruption is applied to read the data thereby recognizing the destination of interruption in high speed. Thus, the polling operating time is reduced remarkably. |
