| 摘要 |
A multi-phase undervoltage detection circuit is disclosed wherein a multi-phase input voltage is compared to a reference. If the peak level of the input voltage is above the reference, a capacitor is discharged. If the voltage of any one of the phases is below the reference, the capacitor charges above the level of the input to a flip-flop. At the same time the voltage of another of the phases clocks the flip-flop. Since the input of the flip-flop is "high" when it is clocked, it changes states and its output goes "low" which provides a circuit output indicative of an undervoltage condition. If no undervoltage condition exists, the flip-flop will not change states and the circuit output is indicative of a non-undervoltage condition.
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