发明名称 BATTERY SAVING FREQUENCY SYNTHESIZER ARRANGEMENT
摘要 <p>BATTERY SAVING FREQUENCY SYNTHESIZER ARRANGEMENT An arrangement for reducing the amount of battery supplied power to a high frequency synthesizer. The phaselocked loop section of the synthesizer is periodically disconnected from the battery supplied power. In order to prevent substantial drift of the phase-locked loop during such power interruption, means are provided for maintaining a control signal on the VCO associated with the loop that maintains the VCO frequency. By minimizing the frequency drift, the loop can be re-locked in a short period of time following each power interruption.</p>
申请公布号 CA1183911(A) 申请公布日期 1985.03.12
申请号 CA19820403047 申请日期 1982.05.14
申请人 GENERAL ELECTRIC COMPANY 发明人 CHALLEN, RICHARD F.
分类号 H03B21/02;(IPC1-7):H03B21/02 主分类号 H03B21/02
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