发明名称 FAULT CHECKING METHOD
摘要 PURPOSE:To decide the factor of a fault just by switching the state of an input signal after adding signals which are supplied to a control part of a device in a selection mode and providing a display element which displays the result of addition. CONSTITUTION:Binary logic inputs 1-4 are connected to a CPU by signal lines 1a-1b and then connected to the 1-bit (a) half address 2a-2b. The output of addition is impressed to an LED4 via an inverse amplifier 3. The inputs 1-4 are set at 1, 0, 1 and 0 respectively and either one of these inputs is inverted. Thus the output of addition is inverted to turn on the LED4. As a result, the lighting state is changed in response to each input. Thus it is possible to decide a normal or abnormal state of a device.
申请公布号 JPS6043709(A) 申请公布日期 1985.03.08
申请号 JP19830150550 申请日期 1983.08.18
申请人 KONISHIROKU SHASHIN KOGYO KK 发明人 WATANABE KAZUO
分类号 G03G21/00;G06F11/00 主分类号 G03G21/00
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