| 摘要 |
PURPOSE:To shorten the waiting time of a bus and to improve the performance of a processor unit by forming a directory memory access bus contention circuit to provide priority to a bus using request from the processor unit. CONSTITUTION:When a bus using request is generated from the processor unit 13, a bus using permission signal is turned to ''1'' through an AND gate, a J- KFF, etc. in the direct memory access (DMA) bus contention circuit 15 to permit the use of the bus. Even if an I/O 17 or the like outputs a bus using request signal, the bus can not be used until the unit 13 ends the use of the bus. If a bus using request is outputted from the unit 13 again even when the bus using by the unit 13 has been ended and the bus is being used by the I/O 17 or the like, the bus using request from the unit 13 is made prior to other unit. consequently, the bus waiting time can be shortened and the performance of the processor unit 13 can be improved. |
