| 摘要 |
PURPOSE:To reduce the load on an arithmetic processor by limiting the read of an interruption signal by the arithmetic processor and decreasing the frequency of the execution of interruption processing when the arithmetic processor requires no data to be supplied from an external device. CONSTITUTION:When respective slave stations 10 are subjected to centralized control by arithmetic processors 1 and each slave station 10 is put in operation several times a day, data of the respective slave stations 10 should be collected speedily in operation, but need not be collected during their stops. While each slave station 10 is put in operation, the arithmetic processor 1 sets an interruption control signal CS to ''1'' to accept the interruption signal, and when in a stop state, the signal is set to ''0'' and the interruption signal is not accepted. The arithmetic processor 1 has a control register 11 internally and sets or reset a control register 11 according to the contents a cotrol command signal to each slave station 10, thereby generating the interruption signal CS. |
