| 摘要 |
PURPOSE:To interrupt a program without decreasing the speed of execution processing by detecting the coincidence between an address value for the interruption and the address value of the instruction fetch of an execution program. CONSTITUTION:A processor 40 is equipped with an instruction execution part 41, which checks whether an instruction is present in a prefetch queue buffer 43 or not from a queue empty signal 44 from a prefetch control part 42. When the instruction is present, it is prefetched and executed to send specific data to a common bus 1 at specific timing through a bus interface 46, and specific data is fetched from the common bus 1, and decoded and executed. The prefetch control part 42, on the other hand, fetches an instruction when receiving a prefetch start command signal 45 from the instruction execution part 41, but this fetch is performed independently in parallel to the execution processing of the execution part 41. |
