| 摘要 |
PURPOSE:To secure a hold time with one group of clocks by providing a device having a shift register composed of FFs with a circuit which switches input data and shift data, and sending the clocks reversed in phase each other to a master FF and a slave FF. CONSTITUTION:The master FF1 (or FF2) including a data selector circuit latches data DAT1 (or DAT2) externally at a rise of a clock CLK. A clock supplied to the slave FF3 (or FF4) including a data selector circuit, however, is already inverted by an inverter 5, so the outputs of the FFs 1 and 2 are latched at a fall, so that the hold time is secured. When the FF1 (or FF2) is intended to hold its state because trouble occurs to the system, a select signal ENA is held at zero before the next clock CLK falls, and consequently the state of the FF1 (or FF2) is held in an FF3 (or FF4). Then, shifting operation is performed subsequently to read it out as a signal TOUT. |
