FOURIER TRANSFORM PROCESSOR

摘要

PURPOSE:To perform simply a Fourier transform at a high speed and less memory capacity to a data train having the optional bit width, by providing a sequence information generator to a rearranging device to produce the sequence information needed for rearrangement. CONSTITUTION:An output data train delivered from a Fourier transform part 1 is stored to an input memory 2. In this case, the sequence is exchanged with a prescribed relation for said data train. In this respect, the data on the memory 2 are extracted sequentially from the first one and delivered to a rearrangement processor 3 for rearrangement. Furthermore the data delivered from the memory 2 are rearranged and fed to an output memory 4. In this case, the prescribed addresses of the memory 4 are delivered sequentially to the processor 3 from an address generator 6. The procesor 3 writes the data delivered from the memory 2 to the memory 4 by means of the address given from the generator 6. Then the data are rearranged in a regular order.