| 摘要 |
<p>PURPOSE:To improve the accuracy of a bit synchronization clock by frequency- dividing a carrier wave in response to a demodulation signal and obtaining the clock from a frequency-divided output in a device generating the bit synchronization clock from a signal wave applied with the FSK modulation by a split phase code. CONSTITUTION:The signal wave (a) applied with the FSK modulation by the split phase code is demodulated by an FSK demodulating section 5. Moreover, a demodulation signal (b) is set at a mark and a space respectively in counters 6, 7, and the counter 6 frequency-divides the signal wave (a) with a frequency dividing ratio in response to the mark frequency of the FSK signal and the counter 7 frequency-divides the signal wave (a) with the frequency dividing ratio in response to the space frequency. An output (c) of the counter 6 and an output (d) of the counter 7 are synthesized by an OR circuit 8, its sysnthesized signal (e) is frequency-divided by 1/2 by a binary counter 9 to output a synchronized clock signal (f).</p> |
