| 摘要 |
PURPOSE:To recover a data clock with a high rate of convergence and high stability by providing a counter measuring a burst period, a decoder and a logic circuit so as to synchronize an extracted clock and a recovered clock momentarily. CONSTITUTION:A frequency division circuit 1 frequency-divides a basic clock 14 and generates a recovered clock 15. A phase comparison circuit 2 compares the phase of the clock 15 and an extracted clock 16 and outputs the direction of phase shift to a control circuit 3. Further, a counter 4 measures a burst basic period and outputs it to a decoder 5. When the output of the counter reaches a prescribed value or synchronizing step-out signal 17 is made effective, the decoder 5 outputs logic 1 to a logic circuit 6. The logic circuit 6 applies logical operation between the output of the decoder 5 and the clock 16 and generates a reset signal when the output of the decoder 5 and the clock 16 are both logic 1 to reset the counter 4 and the circuit 1 at the same time. Thus, the extracted clock and the recovered clock are synchronized momentarily and the data clock with high convergence and high stability is recovered. |
