发明名称 SEMICONDUCTOR MEMORY
摘要 PURPOSE:To reduce elements of a peripheral circuit attached to each couple of bit lines in number almost to half by uniting a dummy cell and a transistor (TR) for a bit line balance signal with each other. CONSTITUTION:A bit line balance circuit BB is constituted by connecting the drains of TRs (T1 and T2) to a couple of bit lines B0 and B1 and also connecting dummy word lines PB0 and PB1 to the gates of the T1 and T2 which are connected in common at the sources. Then, a reference capacitor CR which is connected to the common source of the T1 and T2 has the other terminal connected to a signal line RE for reference level generation. Thus, the dummy cell and TR for the bit line balance signal are formed in one body to reduce the number of elements in the peripheral circuit attached to each couple of bit lines almost to half.
申请公布号 JPS6020389(A) 申请公布日期 1985.02.01
申请号 JP19830128420 申请日期 1983.07.14
申请人 NIPPON DENKI KK 发明人 TAKESHIMA TOSHIO
分类号 G11C11/401;G11C11/34;(IPC1-7):G11C11/34 主分类号 G11C11/401
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