| 摘要 |
PURPOSE:To attain high speed operation by eliminating the need for an inverter for the purpose of phase matching of each stage. CONSTITUTION:In the i-th stage and the (i+1)th stage constituting a carry circuit comprising a full adder or the like by a Domino circuit, an N-channel positive logical circuit comprising n11-n15 clipped between a point being pulled up and a point being pulled down by an N-channel transistor (TR) n10 includes an j-digit output C as an input during a sampling period of a P-channel TR p10 during the precharge period of the i-digit, i.e., while a clock phi is 0. Further, in the (i+1)-th digit, a negative logical circuit comprising P-channel TRs p21-p25 clipped between a P-channel TR n20 pulled down for an output point D during the precharge period, i.e., while the clock phi is 0 and a point pulled up by an N- channel TR n20 while the clock phi is logical 1 includes a j-digit output C as the input. The Domino circuit is formed by the positive logical circuit as mentioned above and a negative logical circuit comprising elements being complementary to the elements controlled by the input including at least one output of the said positive logical circuit and costituting the positive logical circuit. |
