| 摘要 |
PURPOSE:To attain high speed operation by using separately a power supply for a common source section and for a source follower section and increasing a potential of the source follower more than the potential of the common source section. CONSTITUTION:The power supply for the common source section and that for the source follower section are used separately and also the relation of Vdd1< Vdd2 is set. When a low level is given to a terminal IN and a low level is given to a drain voltage Vd1N of an FET2, a drain voltage Vd1 of the FET2 is nearly equal to Vdd1. In this case, the time constant tau becomes (1/gm).Cgs.Cgd/(Cgs+ Cgd). In this invention, a gate-drain voltage Vgd becomes Vgd=Vdd1-Vdd2 and a gate-source voltage Vgs becomes Vgs=Vdd1 by selecting voltages as Vdd1< Vdd2, and the relation of junction capacitance Cgs=Cgs(0) and Cgd<Cgd(0) and mutual conductance gm=gm max is obtained, where gm max is a maximum value of the mutual conductance gm obtained by changing a bias voltage of the FET. Thus, since the time constant tau is reduced by decreasing the junction capacitance, i.e., increasing the mutual conductance gm, the high speed BFL is attained. |
