发明名称 MEMORY MONITOR SYSTEM
摘要 PURPOSE:To realize the monitor even to such a fault with which the output of a temporary memory is fixed without increasing the memory capacity, by using a monitor time slot before a write mode to read and write a test signal. CONSTITUTION:In a memory monitor mode the main signal which exchanges a time slot is first connected to a test signal produced by a test signal producing circuit 6 through the 1st selection circuit 23. This test signal is written to a temporary memory RAM1. That is, the test signal is written to an address position formed by a test address counter 8 by the position a monitor time slot before a write mode. The written test signal is read out in the next timing. A pattern collation circuit 7 monitors whether the correct reading/writing is carried out. In such a way, the monitor is possible even to such a fault with which the output of a temporary memory is fixed without increasing the memory capacity by using a monitor time slot before a write mode to read and write the test signal.
申请公布号 JPS6014361(A) 申请公布日期 1985.01.24
申请号 JP19830120313 申请日期 1983.07.04
申请人 NIPPON DENKI KK 发明人 UEKAWA FUKASHI
分类号 G06F5/16;G06F12/16;H04J3/06;H04J3/14;(IPC1-7):G06F12/16;G06F5/06 主分类号 G06F5/16
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