| 摘要 |
PURPOSE:To reduce the rear to be occupied by an output buffer transistor by the increase of the gate length per transistor and unit area by a method wherein the element region of the gate controlled type transistor composed of MOSFET formed on a substrate is split type into a plurality of source and srain electrodes by means of mesh gate electrode wiring material, which regions are then connected with wiring material. CONSTITUTION:The gate electrode wiring material 6 of polycrystalline Si, etc. is formed into a lattice form of squares, and the elements region is split so that the source regions 3 and the drain regions 4 become checkered pattern. In such a manner, the most part under the wiring material 6 is made as an active transistor region, resulting in the increase of the gate length per unit area. Here, the lattice can be also formed into other angular form as well as the form of square; the split regions are connected with the wiring material, and then transistors of large driving power and contained in the small regions of an IC device. |
