Adjustable ratio divider

摘要

The divider is formed by a dividing counter 7 to which an input pulse train is fed via an OR gate 3. The counter 7 has a fixed division ratio and the OR gate is controlled by a logic circuit which receives control pulses and controls the OR gate to remove one pulse from the input pulse train for each control pulse in order to change the overall division ratio of the divider. The invention is particularly suitable as an adjustable ratio divider for use in frequency synthesizers.