| 摘要 |
PURPOSE:To form an LRU managing control circuit with simple and less hardware by providing a replacement bit of log2N respectively to N blocks of buffers and deciding the priority of use in the form of tournament. CONSTITUTION:When a CPU conducts block fetch from the main storage, an address and a data are registered to a TAG1 of a cache and a data buffer and also a block fetch address is registered to a TAG2. When the buffer consists of two blocks, the TAG2 consists of BLK0 and BLK1. They are provided respectively with the replacement bits R0, R1 and when both bits are 00 or 11, the BLK1 is used newly and in other case, the BLK0 is used newly. When the replacement is executed, the present operating career is represented by replacing the replacement bit with the algorithm shown in equations and also the block replaced next is represented. When the buffer consists of N blocks, the number of log2N stages is used. |
