| 摘要 |
PURPOSE:To obtain a semiconductor integrated circuit device integrated with a high reliable system enabled sufficiently to cope with even everlasting trouble by a method wherein CPUs of two pieces are formed in one chip together with an action judgement means and a change-over means. CONSTITUTION:Closing of an electric power source is detected by an electric power source ON and OFF detection circuit 12 to output a signal DET, a reset circuit 14 is reset through an OR gate 16, a CPU1 is made to ON, and when the CPU is normal, a signal DB is generated. The output TIN of an OR gate 15 becomes to ''1'' at the same time, the watch dog timer output TOUT of a system control circuit 13 is made to ''1'', and held as it is during the CPU1 is normal. When the CPU is abnormal, the signal DB is not generated, and the output is made to ''0'' for the prescribed time. When the signal TOUT is ''0'', the output signal BUSEX of an FF17 becomes also to ''0'' to change the prescribed buses ABi, DBj and others over a CPU2 through circuits 19, 20 consisting of buffers. Electric power source voltages VCC, VSS are changed over 21, 22 prior to changing over of the buses, and after a sufficient delay 18, the CPU2 is reset by a reset circuit 14 according to a signal REC. According to this construction, the down of the system can be checked. |
