First-in first-out memory

摘要

A sequential memory (10) includes synchronous write control circuitry (26) and synchronous read control circuitry (22). The synchronous write control circuitry produces an Input Ready (IR) signal synchronous with the WRTCLK signal. The synchronous read control circuitry (22) generates a Output Ready (OR) signal synchronously with the RDCLK signal. A RSAM (read sense amplifier) signal is provided to read the sense amplifier associated with a memory (12) responsive to the RDCLK if a RAMRDY signal indicates that a read from this location may be requested on the next clock cycle.