| 摘要 |
PURPOSE:To facilitate debugging a hierarchically structured program by providing an up/down counter and a break control circuit in a debugging device to make it possible to start debugging in a desired transition state. CONSTITUTION:After ''1'' is set to a prescribed address to be counted up of a bit map memory 20 and is set to a prescribed address to be counted down of a bit map memory 21 through a CPU11 by a key input device 13, a prescribed value is preset to a counter 25. When a CPU2 is operated, the counter 25 is driven by the outputs of bit map memories 20 and 21. When the counted number reaches the preset prescribed value, a carry output from the counter 25 is given to a break control circuit 26. Consequently, the CPU2 is stopped when the control is returned to a main routine from a return instruction of a subroutine, and debugging in the single step mode is possible thereafter. |
