| 摘要 |
PCT No. PCT/JP95/00502 Sec. 371 Date Sep. 2, 1997 Sec. 102(e) Date Sep. 2, 1997 PCT Filed Mar. 20, 1995 PCT Pub. No. WO96/29655 PCT Pub. Date Sep. 26, 1996A transmission apparatus capable of transferring data between a transmitting and a receiving device using a small-scale, low-cost hardware implementation for high-speed data transmission, the apparatus being conducive to reducing the amount of system design work on a target system. The transmitting device sends to the receiving device both data and a reference signal generated by a reference signal generation circuit. On the receiving side, a phase adjustment circuit delays the reference signal and a phase determination/phase amount control circuit brings the delayed signal into phase with a receiving-side clock signal. A data signal group is given the same amount of delay as the reference signal. The scheme allows data signals to be received directly in keeping with the receiving-side clock signal, eliminating the need for strict clock skew management, massive detours of data transmission lines or a wasteful wait time required for signal values to be established. |
