| 摘要 |
PURPOSE:To perform the conversion of information with small length of a bounded bit by using a conversion logic, a latch circuit, a shift register, etc. to have a prescribed combination of DC storage in the bit of the signal obtained after conversion of information and to reduce both DC and low band components. CONSTITUTION:The information given from an input terminal 1 undergoes a prescribed bit shift through a shift register 2 with the pulse of a clock terminal 5. Then the 8-bit information is supplied to a conversion logic 3, and this logic 3 performs the 1:1 conversion and adds the 10-bit information to a shift register 4. The inversion frequency of the signal obtained after the conversion is detected. The outputs Q1-Q3 are applied to latch circuits 61-63, and outputs Q'1- Q'3 of the circuits 61-63 are supplied to the logic 3 in response to said inversion frequency and the inversion frequency stored previously in an RAM. Then the pulse timing is detected by a timing detecting circuit 7 and applied to the logic 3 and the register 4, and the signals obtained after conversion are stored in the 1st-3rd combinations. Thus the DC and low band components are reduced. |
