| 摘要 |
PURPOSE:To set double precision data in one step without increasing the quantity of hardware by extracting the high-order part of a mantissa only and setting the low-order part to 0(zero) when the low-order mantissa of double precision data is not required in relation to the significant digit. CONSTITUTION:When high order bits of double precision data are inputted into a mantissa input controlling circuit 114 from an input signal bus 13, a control signal 246 goes to ''1'' and a try state buffer gate (TSG) 313 is selected by means of a NOR gate 303, and then, 0-31bits of the bus 13 are selected. Thereafter, another control signal 247 goes to ''1'' and TSGs 316, 317, and 319 are selected by means of NOR gates 304 and 306. In addition to the above, the 29-60bits positons of a matissa 125 attain the 32-63bits conditions of an input bus 19 and 61-63bits positions go to ''0''. When 64bit double precision data are simultaneously inputted into the buses 13 and 19 and the low-order mantissa is unnecessary, control signals 248 and 249 go to ''1'' and TSGs 310, 311, 315, 318, and 319 are selected, and then, the matissa of the bus 13 only is extracted and low-order bits are set to ''0''. |
