| 摘要 |
PURPOSE:To enable to attain speeding-up and the reduction of consumed power while maintaining the integration density equal to that of the conventional I<2>L by a method wherein both transistors of PNP and NPN types are constructed by merger as a vertical type proper action transistor, and further the output is led out via a Schottky barrier diode. CONSTITUTION:An N<+> type buried layer 12 is provided in a P<-> type Si substrate 11. This layer 12 is provided with an N<-> layer 13 and P type layer 14 by insulation and isolation from the surroundings by means of an isolation oxide film 15. An N<-> layer 16 is provided in the layer 14. An injector layer 17 made up of a P type diffused region is provided in the N<-> layer 16, and an N<+> diffused layer 18 for electrode lead-out is also provided. The entire surface is covered with an Si oxide film 19, and electrodes 20, 211-213, 22, and 23 are formed at each window section. Here, the electrode 20 is an input electrode and contacts the P type layer 14. The electrodes 211-213 are metallic output electrodes and contact the N<-> layer 13 in Schottky manner. |
