| 摘要 |
PURPOSE:To enable to accurately compensate an ultrafine offset voltage by composing of a control gate for controlling the offset voltage of an MOS transistor and a non-volatile memory connected to the gate. CONSTITUTION:When a voltage higher than a threshold voltage is applied to a gate electrode 34, a region 35 surrounded by a broken line becomes a channel region. Hall voltage terminals 36a-36c are formed on the electrode 34 and under an insulating film to form an ultrafine resistance region. Wiring regions 40-42 for electrically connecting the region 35 an fuse memories 38a-38c are the same conductive type as source region and drain region 31, 33. Numerals 37a-37c are electrode wirings for selecting the Hall voltage detecting terminals 36a-36c. In such a structure, the offset voltage when a magnetic field is 0 can be accurately compensated for the ultrafine offset voltagae produced in the manufacture of an MOS Hall element by selecting the memories 38a-38c.
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