发明名称 CPU BUS CONTROL CIRCUIT
摘要 PURPOSE:To check up to which instruction the circuit is operated normally by interrupting the operation of a device to be tested when a program testing the device to be tested is stored in an ROM and a test instruction is proceeded up to a predetermined address on the ROM. CONSTITUTION:In confirming whether or not instructions until an address [alpha+n] are executed correctly by the device 3 to be tested, a part of a program stored in an ROM2 is replaced into an instruction, e.g., [FF], the address [alpha+n] in set to an address setting circuit 4 and a command to be returned to an address [alpha] is given to a data setting circuit 7. When a CPU1 outputs the [alpha+n] to an address bus 10, a data read from the ROM2 is blocked for its output to a bus 9 and the data [FF] set in advance to the data setting circuit 7 is given on the bus 9. The normal operation of the device to be tested until the [alpha+n] is confirmed in this way.
申请公布号 JPS59225423(A) 申请公布日期 1984.12.18
申请号 JP19830099963 申请日期 1983.06.03
申请人 ALPS DENKI KK 发明人 TOUJIYOU KUNIO
分类号 G06F13/10;G06F3/00;G06F11/22 主分类号 G06F13/10
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