发明名称 DATA TRANSFER SYSTEM
摘要 PURPOSE:To obtain a buffer means if data transfer disable state occurs in a front end and to avoid generation of an I/O error by using a data buffer register of front end in common. CONSTITUTION:Front ends FE#a, FE#b are provided respectively between plural input/output devices i/oa and i/ob and a central operation processor CPU for each input/output device so as to transfer data between the CPU and the i/oa, i/ ob. If one of the plural front ends reaches data transfer disable state, a detecting circuit detects the other fron end taking over the data transfer and an output of a data memory of the faulty front end is connected switchingly to a data buffer register of the other normal front end. Thus, the common use of the data buffer register of the front ends is attained.
申请公布号 JPS59225421(A) 申请公布日期 1984.12.18
申请号 JP19830100587 申请日期 1983.06.06
申请人 FUJITSU KK 发明人 KUBO SHINICHI
分类号 G06F13/12;G06F3/00;G06F13/00 主分类号 G06F13/12
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