| 摘要 |
PURPOSE:To allow the RAM to cope with many LSI logics and to prevent an RAM area from being nullified if the RAM is not required by allowing the RAM in a gate array to be used as an RAM, ROM or PLA random logic. CONSTITUTION:Transfer gates N1, N4 of an ROM in the figure are regarded respectively as one bit of the ROM. The writing of program in this ROM is conducted as follows: When an address line 5 is selected and goes to ''H'' by bringing data lines 9, 14 to ''H'', the gate N1 or N4 is turned on with a bit 15 connected to each line by lines 16, 17, 18 and the data line 9 or 14 holding the level ''H'' goes to ''L'', and the ''H'' level of the data lines 9, 14 is held with the bit 15 not programmed and each level is read on the data lines 9, 14.
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