发明名称 SHIFT REGISTER CIRCUIT USING RAM
摘要 PURPOSE:To obtain a shift register with small area by outputting two continuous addresses of plural units of RAM to read out the data of the RAM of the preceding address and to write the input data to the RAM of the succeeding address. CONSTITUTION:An address recorder 15 produces two continuous address signals with the clock signal applied to a terminal 23 and selects the addresses of RAM 11 and 12 of 1-bit. An input data distributor 13 and an output data selector 15 are actuated by the clock signal and connected to the RAM11 and 12 alternately. Therefore the distributor 13 is connected to the RAM11 when the decoder 15 selects addresses 111 and 121. Then the input data is written to the address 111, and a selector 14 is connected to the RAM12 to read the store data out of the address 121. In such a way, the addresses are successively selected for write/read of data. In such a constitution, it is not needed to make the working speed and the number of RAMs double in comparing with a conventional method using RAM. Thus a shift register using plural units of RAM can be miniaturized.
申请公布号 JPS59223845(A) 申请公布日期 1984.12.15
申请号 JP19830098025 申请日期 1983.06.03
申请人 NIPPON DENKI KK 发明人 NAKA MASAHIRO
分类号 G11C19/00;G06F5/08;G06F5/16;H03K5/135 主分类号 G11C19/00
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