发明名称 DIGITAL CONTROLLER
摘要 PURPOSE:To shorten both the transfer time and the control arithmetic cycle with a digital controller by transferring the past value only with the past value data on a desired arithmetic circuit. CONSTITUTION:A CPU which is under control transfers only the analog and logical intermediate values which require the prescribed past value to a CPU under waiting together with the process control with a process controller containing multiple CPUs. The waiting CPU starts an intermediate value CLA reception task 22 and stores the intermediate value data to a buffer area 25. The waiting CPU performs the arithmetic processing with the control task and then the reception data fetching processing. Then the output value of an integration circuit, etc. is refreshed to the data received from the CPU under control. Thus the next control arithmetic processing is carried out with the refreshed control data value. If the control cycle is sufficiently smaller than the time constant, the approximately equal arithmeric data value is obtained between the control and waiting modes. Thus the bumpless switching is possible for a digital controller.
申请公布号 JPS59221702(A) 申请公布日期 1984.12.13
申请号 JP19830096266 申请日期 1983.05.31
申请人 MITSUBISHI JUKOGYO KK;MITSUBISHI DENKI KK 发明人 KINO ETSUJI;HIRATA DAISAKU;TATSUMI KAZUMA;FURUKUBO YUUJI
分类号 G05B9/03;G05B7/02;(IPC1-7):G05B9/03 主分类号 G05B9/03
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