Floating point addition architecture

摘要

Parallel shifter architecture in an arithmetic unit of a digital computer for processing floating point mantissas. An arithmetic-logic unit (ALU) in series with shifting means functions in parallel with a barrel shifter. Both paths are executed simultaneously and the output of one path is selected for storage at the end of a microcycle based on machine status and the actual floating point numbers manipulated. This architecture provides a significant reduction in floating point addition execution time.