| 摘要 |
PURPOSE:To increase the margin to the fluctuation of a process parameter by increasing the difference between the high and low levels of the potential at an input node of a sense amplifier on a bit line which is decided by the memory contents of a memory cell and slowing the change of the potential of the input node to the potential change of the bit line. CONSTITUTION:A p channel load formed by connecting the gate and the drain of a p channel enhancement type transistor TR40 to each other is used as a load circuit of a bit line of a CMOS EPROM. The high level of the potential VB of a node B rises up to VCC-VTHP (threshold voltage of TR40) in a read mode when a memory cell is under a non-write mode since the p channel load receives no effect of a back gate bias effect. As a result, the difference between the high and low levels of the potential VB is increased. The TR40 works in a saturated area and its conductance is proportional to (VCC-VTHP-Va)<2>. Therefore the change of the VB of the node B is comparatively slow compared with the change of the potential VD of a node D.
|
