发明名称 MEMORY ERROR RELIEVE SYSTEM
摘要 PURPOSE:To relieve a 1-bit memory error without providing any circuit which inhibits the memory access from other processor specially by employing a partial writing system, and reading 1-bit error data and rewriting corrected data in a single-time memory access. CONSTITUTION:A processor 16 sends a read request to a memory device 1 to which data 3 containing a 1-bit error is read out of a storage part 2 in the process of instruction execution, and sets the corresponding address in a memory address register 4, and the memory device 1 reads the data 3 out of the storage part 2 and inputs it to a humming check circuit 15 to detect the 1-bit error and correct the error bit. The processor 16 is informed of the 1-bit error from the memory device 1 through a signal line 9 in the instruction execution process, so the address of the 1-bit error data 3 is fetched from an error address register 5 through a bus 8 after the instruction execution is completed.
申请公布号 JPS59217298(A) 申请公布日期 1984.12.07
申请号 JP19830090978 申请日期 1983.05.24
申请人 NIPPON DENSHIN DENWA KOSHA;NIPPON DENKI KK;HITACHI SEISAKUSHO KK;FUJITSU KK 发明人 HIRANO MASANORI;OONO KUNIO;SUMIMOTO TSUTOMU;OZAKI HISAYASU
分类号 G06F12/16;G06F11/00 主分类号 G06F12/16
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