CONTROL CHANNEL INTERFACE CIRCUIT

摘要

Control channel interface circuit for interfacing a port processor (202) of a distributed multiprocessor communication system (200) to a common time division multiplexed (TDM) bus (A, B). The detection, extraction and synchronization of control messages passed between a central processor and port processor via a TDM bus are handled by the interface unit (203) thereby relieving a port processor of this burden. A group of control time slots within a system frame are dedicated to the transfer of control messages between port processors and a central processor. The interface unit also monitors the operability of a respective port processor and automatically disables a faulty processor.